Phase One combined the low power consumption of the CoolRunner-II CPLD with the functional capabilities of the Virtex-II family.
From casual consumers to experienced professionals, digital photography has changed the way we all think about taking pictures. Indeed, digital cameras are replacing traditional film cameras at a faster rate than ever.
At the same time, digital image quality is improving quickly. Whereas consumer digital cameras typically have around 3 million pixels for an image, professional digital cameras have from 6 million to 22 million pixels.
As such, they present a far greater engineering challenge. Their large image file sizes must be moved quickly to achieve the high frame rates that professionals (such as fashion photographers) require. These cameras must also have advanced image processing capabilities and precise power management to extend battery life and reduce image distortion, which can be caused by thermal noise from high power dissipation of the built-in electronics.
At Phase One, we found a solution to these engineering challenges by incorporating the Xilinx CoolRunner-II™ CPLD and the Virtex™-II FPGA into the design of our digital camera back, the H25.
Modular Camera Design
Figure 1 shows the modular structure of a generic professional-quality, medium-format camera. This modularity allows photographers to not only swap lenses, but to use a different viewfinder or an alternative camera back.
A conventional camera back contains the type of film being used, but Phase One now produces a range of digital camera backs compatible with medium-format camera systems, enabling improved workflow and new creative opportunities. Compared to film, these camera backs also improve image quality and color reproduction.
Technical Requirements
At Phase One, we have created digital imaging solutions for professional photographers since 1993, supplying cameras for medical diagnostics and aerial photography as well as studio and fashion photography. Through the years we have also supplied numerous OEM solutions for technically demanding applications. Our customers demand very high resolution, high sensitivity, ruggedness, reliability, a high continuous capture rate, and perfect color reproduction.
High-end professional film formats are larger than the 35-mm standard. For example, the classic 6 cm x 6 cm Hasselblad™ medium format is a favorite among professional photographers. Newer autofocus cameras from Hasselblad, Contax™, Mamiya™, and Fuji™ use a 6 cm x 4.5 cm format, which has also become popular. These larger film formats enable higherresolution digital camera solutions without compromising image quality, which is highly dependent on pixel size. Larger pixels typically yield higher sensitivity and less noise.
Phase One digital camera backs are now available with image sensors ranging from 6 to 22 megapixels. This enables an active imaging area as large as 48 mm x 36 mm in our flagship H25 digital camera back.
The H25 image sensor is a huge piece of silicon that dwarfs even a large FPGA die. In fact, it is currently one of the world’s largest commercially available imaging sensors, and helps the H25 push digital photography beyond the image quality of traditional film.
The specification for the H25 camera platform included the following key points:
* Huge image file sizes: 128 MB/image allows for 16 bits per color, for a total of 48 bits of red/green/blue (RGB) color depth
* Data moving capability as fast as 7 Gbps
* Big image buffer for long burst sequences
* Storage of uncompressed or losslessly compressed images in the RAW image format to keep the highest possible image quality
* High sustained frame rates with more than 30 frames/minute (faster frame rates are possible when images are captured in a burst)
* High processing power to enable severe image processing and compression
* 400 Mb IEEE1394 connection with proprietary high-speed image data streaming
* Advanced power management to reduce thermal dissipation as well as prolong battery life
* Small physical size.
Hardware Selection
When designing the H25, we used the CoolRunner-II CPLD to implement serial controllers, interrupt controller, and power management functions. We also used the plentiful on-chip resources of the CoolRunner-II device to implement the user interface controller, camera body interface, and glue logic.
The low current draw of the CoolRunner-II CPLD allowed us to minimize power dissipation, extending battery life and reducing the effects of thermal noise on image quality.
The powerful features embedded in the Virtex-II architecture provided even greater opportunities to maximize the performance of the H25, while also meeting important marketing targets.
Apart from restrictions on size, weight, and power, cost is always a concern. Time to market is paramount – the majority of our income from a new camera comes within the first year of its lifetime.
We considered alternatives, including ASIC and other “hard-coded” FPGA technologies. Although these were technically feasible, it was far more cost-effective, easier, and faster to complete the design using Virtex-II FPGAs.
Figure 2 outlines the functional blocks of the Phase One H25 digital camera platform.
Implementing the H25 Camera Platform
We combined the high parallel image processing capability of the Virtex-II on-chip multipliers with the advanced digital clock managers (DCMs) and block RAMs to configure the Virtex-II FPGA as a powerful co-processsor chip. The Virtex-II device had ample capacity to offload most of the high data-rate tasks and image processing.
At the same time, we were able to implement large numbers of customized controllers within the device, thereby reducing the physical size. This also made it extremely easy to interface the central processor to various hardware blocks.
The DCMs are a huge benefit in systems where off-chip and on-chip frequencies are high. They enable easy and flexible de-skewing of board clocks and are very useful, for instance, in high-speed SDRAM controllers. No other FPGA vendor provides such an abundance of DCMs.
This is especially valuable in our application, because we use many different highspeed clocks when interfacing to different sections of the board. It also allowed us to apply a very fine-grained power management structure where various sections can be powered down or slowed to reduce the total power consumption. The H25 continuously adjusts frequencies on-the-fly to fulfill user demands at the lowest power consumption.
Virtex-II’s SelectIO™+ technology supports high-speed signaling standards. We used these to move data onto and off the chip at 7 Gbps.
However, internal bandwidth is much higher if you consider all parallel processes that use local storage. We therefore used the Virtex-II block RAMs to implement various first in first outs (FIFOs), to handle data movement across different clock domains and on-chip local data caches. On-chip caches are absolutely essential for implementing high-speed image processing algorithms as well as advanced image compression.
By moving these functions into the Virtex-II FPGA, we also freed the main processor to execute real-time operating system (RTOS)-based system controller functions. This created a system performance overhead that can support additional functionality as market requirements increase. We can also upgrade products already in the field, adding new functions as we develop them.
Virtex-II’s in-field reprogramming is crucial to this capability because it implements so much of the camera’s functionality. This easy upgrade path also helps win loyalty from photographers, who see value in receiving ongoing improvements. We can keep ahead of our competition without having to release a totally new product every month. And we can assure our customers that they will always have a superior camera.
Conclusion
At Phase One we are committed to staying ahead of the competition, with excellent image fidelity in the field of digital highend imaging. We hope to continue to push digital imaging beyond current technical boundaries.
The current trend towards breaking down the barriers between embedded software and hardware will help us to continuously exploit the technical capabilities of Xilinx FPGAs and CPLDs to achieve this ambitious goal.
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